Vacancy No. IPE 15-20
IPE 15-20 Masterthesis: Development of a novel Time-to-digital converter FPGA architecture using machine learning
Time-to-Digital converters (TDCs) are widely used in high-energy physics and other applications that require precise time measurements. Field programmable gate arrays (FPGAs) can be used to realize TDCs without any external circuits. Current TDCs are based on tapped delay lines (TDL). There are two major issues with the design of this delay lines in FPGA. Delay bins are not uniform and strongly dependant on temperature and voltage level. To compensate this effect and improve the time resolution the bin widths must be calibrated online. This thesis focusses on a novel TDC architecture where the digital electronics, employed for both decoding and on-line calibrations, is replaced by a machine learning algorithm, which extracts the digital information directly from the TDLs. The goal is to measure time-of-arrive and length of pulses with picosecond time resolution.
- Study the current TDC architectures
- Develop a novel TDC architecture with machine-learning with an ZYNQ US++
- Train the neural network on the ZYNQ US++
- Characterization with fast detectors
- Knowledge in Machine learning and Verilog/VHDL (basic)
- Embedded and hardware programming (better but not required)
- Previous experience with developing for a Xilinx Zynq SoC (better but not required)
Institute for Data Processing and Electronics (IPE)
as soon as possible
limited regarding study regulations
Contact person in line-management
Dr.-Ing. Michele Caselle (IPE) (0721 / 608 25903),
Please apply online using the button below for this vacancy number IPE 15-20.
Personnel support is provided by
phone: +49 721 608-25184,
Hermann-von-Helmholtz-Platz 1, 76344 Eggenstein-Leopoldshafen, Germany
Recognized severely disabled persons will be preferred if they are equally qualified.